T1040/T1042 QorIQTM Advanced Multiprocessing Processors Class Dates Offered: May 2 to May 6, 2016 in SAn Jose, CA PLEASE CONTACT ARNEWSH INC. FOR ONSITE TRAINING THIS CLASS IS AVAILABLE TO THOSE HAVING NDA WITH FREESCALE SEMICONDUCTOR FOR T1040/1042
Description:	This is a 5-day class covering the hardware and software aspects of the QorIQ T1040/1042 advanced Multiprocessing Processors. A customized, shorter version can be arranged for on-site training. Students will learn to design and write programs for various chip sub-modules. This includes the embedded Power Architecture Cores (64-bit e5500 with MMU and Caches), Buffer Manger, Queue Manager, PAMU, Frame Manager (icluding Parser, KeyGen, Coarse Classifier, and Policer), PCI Express, DMA controllers, Integrated Flash Controller, DDR3L/4 Controller, Reset, configuration and Interrupt Controller.
Objectives:	Learn the architecture of e5500 core Configure MMU and set up caches (L1, L2, and L3) Learn the exception processing in e5500 Configure the interrupt controller Reset and hardware configuration of the T1040/T1042 Configure Peripheral Access Management Unit (PAMU) Configure and use Buffer Manager (BMan) Configure and use Queue Manager (QMan) Configure and use Frame Manager (FMan), Parser, KeyGen, Coarse Classifier, and Policer Configure and use DMA Controllers Configure and use PCI Express Configure Integrated Flash Controller Configure the DDR3L/4 Controller
Prerequisites:	To benefit most from the course, familiarity with the Power Architecture is recommended. On-site classes can be customized to exclude topics which are not of interest.
back to	TechnicalTraining