P1021/P1012 QorIQTM Integrated Processors Class Dates Offered: No open class scheduled at this time PLEASE CONTACT ARNEWSH INC. FOR ONSITE TRAINING
Description:	This is a 5-day class covering hardware and software aspects of the QorIQ P1021/P1012 integrated processors. A customized, shorter version can be arranged for on-site training. Students will learn to design and write programs for various chip sub-modules. This includes the embedded Power Architecture Cores (e500v2 with MMU and Caches), Enhansed Local bus, PCI Express, Enhanced Three Speed Ethernet Controllers, DMA controllers, DDRII/III Controller, QUICC Engine, Reset and configuration and Interrupt Controller.
Objectives:	Learn the architecture of e500v2 core Configure MMU and set up caches (L1 and L2) Learn the exception processing in e500v2 Configure the interrupt controller Configure Enhanced Local bus memory controller Configure the DDRII/III controller Configure and use the Enhanced Three Speed Ethernet Controller Configure and use PCI Express Reset and hardware configuration of the P1021/12 processors Configure and use the QUICC Engine Configure and use the UCC for slow protocol (UART example) Configure and use the UCC for fast protocol (Ethernet example)
Prerequisites:	To benefit most from the course, familiarity with the Power Architecture is recommended. On-site classes can be customized to exclude topics which are not of interest.
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